A Highly Integrated Adiabatic Energy Recovery

A low-power high-resolution digital input display architecture has been developed which is scaleable to larger display resolutions and grayscale resolutions. The architecture uses parallel sampled ramp DACs in a one-per-column configuration. Both adiabatic and energy recovery operation modes are incorporated for low power. This architecture allows the implementation of optimal drive schemes which are too power intensive when implemented on conventional displays. A 160 x 120 pixel 6-bit implementation of the architecture has been fabricated and tested; it consumes 7.5 imiW (worst case) with a 4 MHz pixel clock. A theoretical power consumption model is validated by the working implementation and used to predict the power for other display resolutions, grayscale resolutions, and driving schemes. Thesis Supervisor: Thomas F. Knight Jr. Title: Senior Research Scientist